Chapter 1 Models for Integrated-Circuit Active Devices 1

1.1 Introduction 1

1.2 Depletion Region of a pn Junction 1

1.2.1 Depletion-Region Capacitance 5

1.2.2 Junction Breakdown 7

1.3 Large-Signal Behavior of Bipolar Transistors 9

1.3.1 Large-Signal Models in the Forward-Active Region 9

1.3.2 Effects of Collector Voltage on Large-Signal Characteristics in the Forward-Active Region 14

1.3.3 Saturation and Inverse-Active Regions 16

1.3.4 Transistor Breakdown Voltages 21

1.3.5 Dependence of Transistor Current Gain ß F on Operating Conditions 24

1.4 Small-Signal Models of Bipolar Transistors 26

1.4.1 Transconductance 26

1.4.2 Base-Charging Capacitance 28

1.4.3 Input Resistance 29

1.4.4 Output Resistance 30

1.4.5 Basic Small-Signal Model of the Bipolar Transistor 30

1.4.6 Collector-Base Resistance 31

1.4.7 Parasitic Elements in the Small-Signal Model 31

1.4.8 Specification of Transistor Frequency Response 35

1.5 Large-Signal Behavior of Metal-Oxide-Semiconductor Field-Effect Transistors 39

1.5.1 Transfer Characteristics of MOS Devices 39

1.5.2 Comparison of Operating Regions of Bipolar and MOS Transistors 46

1.5.3 Decomposition of Gate-Source Voltage 48

1.5.4 Threshold Temperature Dependence 48

1.5.5 MOS Device Voltage Limitations 49

1.6 Small-Signal Models of MOS Transistors 50

1.6.1 Transconductance 51

1.6.2 Intrinsic Gate-Source and Gate-Drain Capacitance 52

1.6.3 Input Resistance 53

1.6.4 Output Resistance 53

1.6.5 Basic Small-Signal Model of the MOS Transistor 53

1.6.6 Body Transconductance 54

1.6.7 Parasitic Elements in the Small-Signal Model 55

1.6.8 MOS Transistor Frequency Response 57

1.7 Short-Channel Effects in MOS Transistors 60

1.7.1 Velocity Saturation from the Horizontal Field 60

1.7.2 Transconductance and Transition Frequency 64

1.7.3 Mobility Degradation from the Vertical Field 66

1.8 Weak Inversion in MOS Transistors 67

1.8.1 Drain Current in Weak Inversion 67

1.8.2 Transconductance and Transition Frequency in Weak Inversion 70

1.9 Substrate Current Flow in MOS Transistors 73

A.1.1 Summary of Active-Device Parameters 74

Problems 76

References 78

General References 79

Chapter 2 Bipolar, MOS, and BiCMOS Integrated-Circuit Technology 81

2.1 Introduction 81

2.2 Basic Processes in Integrated-Circuit Fabrication 82

2.2.1 Electrical Resistivity of Silicon 82

2.2.2 Solid-State Diffusion 83

2.2.3 Electrical Properties of Diffused Layers 85

2.2.4 Photolithography 87

2.2.5 Epitaxial Growth 89

2.2.6 Ion Implantation 90

2.2.7 Local Oxidation 90

2.2.8 Polysilicon Deposition 90

2.3 High-Voltage Bipolar Integrated-Circuit Fabrication 91

2.4 Advanced Bipolar Integrated-Circuit Fabrication 95

2.5 Active Devices in Bipolar Analog Integrated Circuits 98

2.5.1 Integrated-Circuit npn Transistors 99

2.5.2 Integrated-Circuit pnp Transistors 111

2.6 Passive Components in Bipolar Integrated Circuits 118

2.6.1 Diffused Resistors 119

2.6.2 Epitaxial and Epitaxial-Pinch Resistors 122

2.6.3 Integrated-Circuit Capacitors 124

2.6.4 Zener Diodes 124

2.6.5 Junction Diodes 125

2.7 Modifications to the Basic Bipolar Process 127

2.7.1 Dielectric Isolation 127

2.7.2 Compatible Processing for High-Performance Active Devices 128

2.7.3 High-Performance Passive Components 131

2.8 MOS Integrated-Circuit Fabrication 131

2.9 Active Devices in MOS Integrated Circuits 135

2.9.1 n-Channel Transistors 135

2.9.2 p-Channel Transistors 148

2.9.3 Depletion Devices 148

2.9.4 Bipolar Transistors 149

2.10 Passive Components in MOS Technology 150

2.10.1 Resistors 150

2.10.2 Capacitors in MOS Technology 152

2.10.3 Latchup in CMOS Technology 155

2.11 BiCMOS Technology 156

2.12 Heterojunction Bipolar Transistors 157

2.13 Interconnect Delay 160

2.14 Economics of Integrated-Circuit Fabrication 160

2.14.1 Yield Considerations in Integrated-Circuit Fabrication 161

2.14.2 Cost Considerations in Integrated-Circuit Fabrication 163

A.2.1 Spice Model-Parameter Files 166

Problems 167

References 170

Chapter 3 Single-Transistor and Multiple-Transistor Amplifiers 173

3.1 Device Model Selection for Approximate Analysis of Analog Circuits 174

3.2 Two-Port Modeling of Amplifiers 175

3.3 Basic Single-Transistor Amplifier Stages 177

3.3.1 Common-Emitter Configuration 178

3.3.2 Common-Source Configuration 182

3.3.3 Common-Base Configuration 186

3.3.4 Common-Gate Configuration 189

3.3.5 Common-Base and Common-Gate Configurations with Finite r o 191

3.3.6 Common-Collector Configuration (Emitter Follower) 195

3.3.7 Common-Drain Configuration (Source Follower) 198

3.3.8 Common-Emitter Amplifier with Emitter Degeneration 201

3.3.9 Common-Source Amplifier with Source Degeneration 204

3.4 Multiple-Transistor Amplifier Stages 206

3.4.1 The CC-CE, CC-CC, and Darlington Configurations 206

3.4.2 The Cascode Configuration 210

3.4.3 The Active Cascode 214

3.4.4 The Super Source Follower 216

3.5 Differential Pairs 219

3.5.1 The dc Transfer Characteristic of an Emitter-Coupled Pair 219

3.5.2 The dc Transfer Characteristic with Emitter Degeneration 221

3.5.3 The dc Transfer Characteristic of a Source-Coupled Pair 222

3.5.4 Introduction to the Small-Signal Analysis of Differential Amplifiers 225

3.5.5 Small-Signal Characteristics of Balanced Differential Amplifiers 228

3.5.6 Device Mismatch Effects in Differential Amplifiers 235

A.3.1 Elementary Statistics and the Gaussian Distribution 250

Problems 253

References 257

Chapter 4 Current Mirrors, Active Loads, and References 259

4.1 Introduction 259

4.2 Replica Biasing 259

4.3 Current Mirrors 261

4.3.1 General Properties 261

4.3.2 Simple Current Mirror 263

4.3.3 Simple Current Mirror with Beta Helper 269

4.3.4 Simple Current Mirror with Degeneration 270

4.3.5 Cascode Current Mirror 272

4.3.6 Wilson Current Mirror 283

4.4 Active Loads 287

4.4.1 Motivation 287

4.4.2 Common-Emitter-Common-Source Amplifier with Complementary Load 288

4.4.3 Common-Emitter-Common-Source Amplifier with Depletion Load 291

4.4.4 Common-Emitter-Common-Source Amplifier with Diode-Connected Load 293

4.4.5 Differential Pair with Current-Mirror Load 296

4.5 Voltage and Current References 309

4.5.1 Low-Current Biasing 309

4.5.2 Supply-Insensitive Biasing 315

4.5.3 Temperature-Insensitive Biasing 327

A.4.1 Matching Considerations in Current Mirrors 338

A.4.1.1 Bipolar 338

A.4.1.2 Mos 340

A.4.2 Input Offset Voltage of a Differential Pair with Active Load 343

A.4.2.1 Bipolar 343

A.4.2.2 Mos 345

Problems 348

References 353

Chapter 5 Output Stages 355

5.1 Introduction 355

5.2 The Emitter Follower as an Output Stage 355

5.2.1 Transfer Characteristics of the Emitter-Follower 356

5.2.2 Power Output and Efficiency 359

5.2.3 Emitter-Follower Drive Requirements 366

5.2.4 Small-Signal Properties of the Emitter Follower 366

5.3 The Source Follower as an Output Stage 368

5.3.1 Transfer Characteristics of the Source Follower 368

5.3.2 Distortion in the Source Follower 370

5.3.3 Transfer Characteristics of the Super Source Follower 374

5.4 Class B Push-Pull Output Stage 378

5.4.1 Transfer Characteristic of the Class B Stage 378

5.4.2 Power Output and Efficiency of the Class B Stage 381

5.4.3 Practical Realizations of Class B Complementary Output Stages 385

5.4.4 All-npn Class B Output Stage 392

5.4.5 Quasi-Complementary Output Stages 394

5.4.6 Overload Protection 397

5.5 CMOS Class AB Output Stages 399

5.5.1 Common-Drain Configuration 399

5.5.2 Common-Source Configuration with Error Amplifiers 401

5.5.3 Alternative Configurations 408

Problems 415

References 420

Chapter 6 Operational Amplifiers with Single-Ended Outputs 421

6.1 Applications of Operational Amplifiers 422

6.1.1 Basic Feedback Concepts 422

6.1.2 Inverting Amplifier 423

6.1.3 Noninverting Amplifier 425

6.1.4 Differential Amplifier 425

6.1.5 Nonlinear Analog Operations 426

6.1.6 Integrator, Differentiator 427

6.1.7 Internal Amplifiers 428

6.2 Deviations from Ideality in Real Operational Amplifiers 436

6.2.1 Input Bias Current 437

6.2.2 Input Offset Current 437

6.2.3 Input Offset Voltage 438

6.2.4 Common-Mode Input Range 438

6.2.5 Common-Mode Rejection Ratio (cmrr) 439

6.2.6 Power-Supply Rejection Ratio (psrr) 440

6.2.7 Input Resistance 441

6.2.8 Output Resistance 442

6.2.9 Frequency Response 442

6.2.10 Operational-Amplifier Equivalent Circuit 442

6.3 Basic Two-Stage MOS Operational Amplifiers 443

6.3.1 Input Resistance, Output Resistance, and Open-Circuit Voltage Gain 444

6.3.2 Output Swing 446

6.3.3 Input Offset Voltage 446

6.3.4 Common-Mode Rejection Ratio 450

6.3.5 Common-Mode Input Range 451

6.3.6 Power-Supply Rejection Ratio (psrr) 453

6.3.7 Effect of Overdrive Voltages 458

6.3.8 Layout Considerations...