Sanjay Churiwala is an Electronics Engineer from IIT Kharagpur, with two decades of experience in EDA and VLSI. His interest areas include rule checking, synthesis, simulation, STA, Power and Clock Domain Crossings and Synchronization. He currently works at Hyderabad office of Xilinx.

Sridhar Gangadharan is a Senior Product Engineering Director for Timing Constraints Analysis and SpyGlass RTL Analysis Products at Atrenta. He has over 20 years of experience in the electronic design automation industry. His interest areas include RTL verification, timing closure, delay calculation and memory compilers. He holds a Bachelors degree in Computer Science and Engineering from Indian Institute of Technology in Delhi. He is based in San Jose, CA.

Provides a hands-on guide to create constraints for synthesis and timing analysis, using Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints

Explains fundamental concepts around SDC constraints and its application in a design

Explains SDC command syntax, semantics and options

Includes key topics of interest to a synthesis, static timing analysis or place and route engineer

Explains which constraints command to use for ease of maintenance and reuse, given several options possible to achieve the same effect on timing

Includes supplementary material: [...]

Introduction.- Synthesis Basics.- Timing Analysis and Constraints.- SDC Extensions through Tcl.- Clocks.- Generated Clocks.- Clock Groups.- Other Clock Characteristics.- Port Delays.- Completing Port Constraints.- False Paths.- Multi Cycle Paths.- Combinatorial Paths.- Modal Analysis.- Managing Your Constraints.- Miscellaneous SDC Commands.- XDC: Xilinx Extensions To SDC.