Designing with Xilinx® FPGAs

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Beschreibung

This book helps readers to implement their designs on Xilinx® FPGAs. The authors demonstrate how to get the greatest impact from using the Vivado® Design Suite, which delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. This book is a hands-on guide for both users who are new to FPGA designs, as well as those currently using the legacy Xilinx tool set (ISE) but are now moving to Vivado. Throughout the presentation, the authors focus on key concepts, major mechanisms for design entry, and methods to realize the most efficient implementation of the target design, with the least number of iterations.

Über den Autor

Sanjay Churiwala is Senior Director of Engineering for Xilinx India Technology Services. He has extensive experience in the field of EDA and semiconductors R&D, as well as customer-interaction. He specializes in Clock Domain Crossings and Synchronization, STA, Power, Synthesis, Simulation, Rule based static checkers, Cell Characterization and Modeling.

Zusammenfassung

Emphasizes concepts, particularly which device characteristics are important, and how they influence a user's design realization

Uses a systematic approach to achieving design target goals, such as Power and Timing

Explores the various ways to enter design information and read back/analyze a design realization

Demonstrates use of some of the most widely used IP Cores

Explains debugging of designs on Xilinx devices and using Xilinx Tools

Includes supplementary material: [...]

Inhaltsverzeichnis

State of the Art Programmable Logic.- Vivado Design Tools.- IP Flows.- Gigabit Transceivers.- Memory Controllers.- Processor Options.- Vivado IP Integrator.- SysGen for DSP.- Synthesis.- C Based Design.- Simulation.- Clocking.- Stacked Silicon Interconnect.- Timing Closure.- Power Analysis and Optimization.- System Monitor.- Hardware Debug.- Emulation Using FPGAs.- Partial Reconfiguration & Hierarchical Design.

Details

Erscheinungsjahr:	2016
Fachbereich:	Nachrichtentechnik
Genre:	Technik
Rubrik:	Naturwissenschaften & Technik
Medium:	Buch
Inhalt:	x 260 S. 138 s/w Illustr. 3 farbige Illustr. 260 p. 141 illus. 3 illus. in color.
ISBN-13:	9783319424378
ISBN-10:	3319424378
Sprache:	Englisch
Herstellernummer:	978-3-319-42437-8
Ausstattung / Beilage:	HC runder Rücken kaschiert
Einband:	Gebunden
Autor:	Churiwala, Sanjay
Redaktion:	Churiwala, Sanjay
Herausgeber:	Sanjay Churiwala
Auflage:	1st ed. 2017
Hersteller:	Springer Nature Switzerland Springer International Publishing Springer International Publishing AG
Maße:	241 x 160 x 21 mm
Von/Mit:	Sanjay Churiwala
Erscheinungsdatum:	03.11.2016
Gewicht:	0,576 kg

Artikel-ID: 107782691