Weng Fook Lee is a distinguished Technical Director at Emerald Systems Design Center with 25 years of IC Design experience. Lee has vast experience in designing with Verilog and VHDL, and is an internationally acknowledged expert in the field of RTL coding and logic synthesis for ASIC/FPGA/SOC. Lee is an expert in synthesizing and tweaking synthesis for performance and low power, leading enhanced methodology to address advanced DFT techniques for VDSM technology, development and deployment of low power standard cell libraries. Lee have lead the development of new architectures and micro-architectures for efficient PMSM motion control ASIC and have developed architectures for AI classification algorithms implementation in ASIC. Lee published"VHDL Coding and Logic Synthesis with Synopsys" with Academic Press Publication, US (ISBN: 0-12-440651-3) in May 2000, "Verilog Coding for Logic Synthesis" with John Wiley Publication, US (ISBN: 0-471-42976-7) in April 2003, "VLIW Microprocessor Hardware Design for ASICs and FPGA" with McGraw Hill Publication, US (ISBN: 978-[...]) in Aug 2007. Lee is also the inventor and co-inventor of 14 design patents granted by the US Patent and Trademark Office.

Addresses practical design issues and their workarounds

Discusses issues such as CDC, crossing clock domain in shift, scan chains across power domain, timing optimization, standard cell library influence on synthesis, DFT, code coverage, state machine

Provides readers with an RTL coding guideline, based on real experience

Chapter 1. Introduction.- Chapter 2. Design Methodology and Flow.- Chapter 3. Multiple Clock Design.- Chapter 4. Latch Inference.- Chapter 5. Design for Test.- Chapter 6. Signed Verilog.- Chapter 7. State Machine.- Chapter 8. RTL Coding Guideline.- Chapter 9. Code Coverage.