Swarup Bhunia is apreeminence professor and Steve Yaturo Faculty Fellow of Electrical and Computer Engineering in the University of Florida. Earlier he served as the T. and A. Schroeder associate professor of Electrical Engineering and Computer Science at Case Western Reserve [...] has over twenty years of research and development experience with over 250 publications in peer-reviewed journals and premier conferences and eight books (seven edited) in the area of VLSI design, CAD and test techniques. His research interests include hardware security and trust, low power and robust design, adaptive nanocomputing and novel test methodologies. He has worked in the semiconductor industry on RTL synthesis, verification, and low power design for about four years. Dr. Bhunia received IBM Faculty Award (2013), National Science Foundation (NSF) career development award (2011), Semiconductor Research Corporation (SRC) technical excellence award (2005) as a team member, and several best paper awards and nominations. He received his B.E. (Hons.) from Jadavpur University, Kolkata and Master's degree from the Indian Institute of Technology (IIT), Kharagpur. He received his Ph.D. from Purdue University, IN, USA, in 2005. He is a senior member of IEEE.

Mark M. Tehranipoor is currently the Intel Charles E. Young Professor in Cybersecurity at the Department of Electrical and Computer Engineering, the University of Florida. His current research projects include: hardware security and trust, IoT Security, electronics supply chain security, counterfeit IC detection and prevention, and reliable and testable VLSI design. Prof. Tehranipoor has published over 30 journal articles and refereed conference papers and has given more than 170 invited talks and keynote addresses since 2006. In addition, he has published eight books and more than twenty book chapters. His projects are sponsored by both the industry (Semiconductor Research Corporation (SRC), Texas Instruments, Freescale, Comcast, Honeywell, LSI, Mentor Graphics, Juniper, R3Logic, Cisco, Qualcomm, MediaTeck, etc.) and the Government (NSF, ARO, MDA, DOD, AFOSR, DOE, etc.). Prior to joining University of Florida, Dr. Tehranipoor served as the founding director of the Center for Hardware Assurance, Security, and Engineering (CHASE) and the Comcast Center of Excellence in Security Innovation (CSI) at the University of Connecticut. Prof. Tehranipoor is a Senior Member of the IEEE, Golden Core Member of IEEE Computer Society, and Member of ACM and ACM SIGDA. He is also a member of Connecticut Academy of Science and Engineering (CASE).

Explains details of hardware Trojan attacks and associated trust issues, including threat models/instances, attack surfaces, adversaries, and all sorts of protection approaches

Covers Trojan threats and protection approaches at all levels of hardware abstraction, from intellectual Property (IP) to microchip to Printed Circuit Board (PCB) and for all types of electronic hardware including analog/mixed-signal systems and FPGA

Presents taxonomies for hardware Trojan threats, Trojan models, trust benchmarks, and trust metrics

Offers realistic solutions for hardware Trojan threats in industry and government

Describes emerging trend in trustworthy hardware design and new research directions

Part I. Hardware Trojan Preliminaries.- Chapter 1.Introduction.- Chapter 2.Introduction to Hardware Trojans.- Part II. Hardware Trojan attacks: Threat Analysis.- Chapter 3.Hardware Trojan Attacks in SoC and NoC.- Chapter 4. Hardware IP Trust.- Chapter 5. Hardware Trojans in Analog, Mixed-Signal and RF ICs.- Chapter 6. Hardware Trojans and Piracy of PCBs.- Part III. Detection-Logic Testing.- Chapter 7. Logic Testing for Hardware Trojan Detection.- Chapter 8. Formal Approaches to Hardware Trust Verification.- Chapter 9. Golden-free Trojan Detection.- Part IV-Detection-Side Channel analysis.- Chapter 10. Detecting Hardware Trojans using Delay Analysis.- Chapter 11. Reverse-Engineering Based Hardware Trojan Detection.- Part VI. Emerging Trent, Inductrial Practices, New Attacks.- Chapter 15. Hardware Trust in Industrial SoC Designs: Practice and Challenges.- Chapter 16.Conclusion and Future Work.