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Timing
Taschenbuch von Sachin Sapatnekar
Sprache: Englisch

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Beschreibung
Statistical timing analysis is an area of growing importance in nanometer te- nologies¿ as the uncertainties associated with process and environmental var- tions increase¿ and this chapter has captured some of the major efforts in this area. This remains a very active field of research¿ and there is likely to be a great deal of new research to be found in conferences and journals after this book is published. In addition to the statistical analysis of combinational circuits¿ a good deal of work has been carried out in analyzing the effect of variations on clock skew. Although we will not treat this subject in this book¿ the reader is referred to [LNPS00¿ HN01¿ JH01¿ ABZ03a] for details. 7 TIMING ANALYSIS FOR SEQUENTIAL CIRCUITS 7.1 INTRODUCTION A general sequential circuit is a network of computational nodes (gates) and memory elements (registers). The computational nodes may be conceptualized as being clustered together in an acyclic network of gates that forms a c- binational logic circuit. A cyclic path in the direction of signal propagation 1 is permitted in the sequential circuit only if it contains at least one register . In general, it is possible to represent any sequential circuit in terms of the schematic shown in Figure 7.1, which has I inputs, O outputs and M registers. The registers outputs feed into the combinational logic which, in turn, feeds the register inputs. Thus, the combinational logic has I + M inputs and O + M outputs.
Statistical timing analysis is an area of growing importance in nanometer te- nologies¿ as the uncertainties associated with process and environmental var- tions increase¿ and this chapter has captured some of the major efforts in this area. This remains a very active field of research¿ and there is likely to be a great deal of new research to be found in conferences and journals after this book is published. In addition to the statistical analysis of combinational circuits¿ a good deal of work has been carried out in analyzing the effect of variations on clock skew. Although we will not treat this subject in this book¿ the reader is referred to [LNPS00¿ HN01¿ JH01¿ ABZ03a] for details. 7 TIMING ANALYSIS FOR SEQUENTIAL CIRCUITS 7.1 INTRODUCTION A general sequential circuit is a network of computational nodes (gates) and memory elements (registers). The computational nodes may be conceptualized as being clustered together in an acyclic network of gates that forms a c- binational logic circuit. A cyclic path in the direction of signal propagation 1 is permitted in the sequential circuit only if it contains at least one register . In general, it is possible to represent any sequential circuit in terms of the schematic shown in Figure 7.1, which has I inputs, O outputs and M registers. The registers outputs feed into the combinational logic which, in turn, feeds the register inputs. Thus, the combinational logic has I + M inputs and O + M outputs.
Zusammenfassung
Provides an in-depth treatment of the analysis of interconnect systems, static timing analysis for combinational circuits, timing analysis for sequential circuits, and timing optimization techniques at the transistor and layout levels
Inhaltsverzeichnis
Preduction/Introface.- A Quick Overview of Circuit Simulation.- Frequency-Domain Analysis of Linear Systems.- Timing Analysis for a Combinational Stage.- Timing Analysis for Combinational Circuits.- Statistical Static Timing Analysis.- Timing Analysis for Sequential Circuits.- Transistor-Level Combinational Timing Optimization.- Clocking and Clock Skew Optimization.- Retiming.- Conclusion.
Details
Erscheinungsjahr: 2010
Fachbereich: Nachrichtentechnik
Genre: Technik
Rubrik: Naturwissenschaften & Technik
Medium: Taschenbuch
Inhalt: xii
294 S.
68 s/w Illustr.
ISBN-13: 9781441954084
ISBN-10: 1441954082
Sprache: Englisch
Ausstattung / Beilage: Paperback
Einband: Kartoniert / Broschiert
Autor: Sapatnekar, Sachin
Auflage: Softcover reprint of the original 1st ed. 2004
Hersteller: Springer US
Springer US, New York, N.Y.
Maße: 235 x 155 x 17 mm
Von/Mit: Sachin Sapatnekar
Erscheinungsdatum: 07.12.2010
Gewicht: 0,476 kg
Artikel-ID: 107251631
Zusammenfassung
Provides an in-depth treatment of the analysis of interconnect systems, static timing analysis for combinational circuits, timing analysis for sequential circuits, and timing optimization techniques at the transistor and layout levels
Inhaltsverzeichnis
Preduction/Introface.- A Quick Overview of Circuit Simulation.- Frequency-Domain Analysis of Linear Systems.- Timing Analysis for a Combinational Stage.- Timing Analysis for Combinational Circuits.- Statistical Static Timing Analysis.- Timing Analysis for Sequential Circuits.- Transistor-Level Combinational Timing Optimization.- Clocking and Clock Skew Optimization.- Retiming.- Conclusion.
Details
Erscheinungsjahr: 2010
Fachbereich: Nachrichtentechnik
Genre: Technik
Rubrik: Naturwissenschaften & Technik
Medium: Taschenbuch
Inhalt: xii
294 S.
68 s/w Illustr.
ISBN-13: 9781441954084
ISBN-10: 1441954082
Sprache: Englisch
Ausstattung / Beilage: Paperback
Einband: Kartoniert / Broschiert
Autor: Sapatnekar, Sachin
Auflage: Softcover reprint of the original 1st ed. 2004
Hersteller: Springer US
Springer US, New York, N.Y.
Maße: 235 x 155 x 17 mm
Von/Mit: Sachin Sapatnekar
Erscheinungsdatum: 07.12.2010
Gewicht: 0,476 kg
Artikel-ID: 107251631
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